Circuitos Digitales - monitor en vhdl

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MonitorController is

    Port ( clk : in STD_LOGIC;

           reset : in STD_LOGIC;

           h_sync : out STD_LOGIC;

           v_sync : out STD_LOGIC;

           pixel_out : out STD_LOGIC_VECTOR(7 downto 0));

end MonitorController;

architecture Behavioral of MonitorController is

    -- Declaración de constantes para resolución y sincronización

    constant H_SYNC_CYCLES : natural := 96;

    constant H_BACK_PORCH : natural := 48;

    constant H_ACTIVE_VIDEO : natural := 640;

    constant H_FRONT_PORCH : natural := 16;

    constant V_SYNC_CYCLES : natural := 2;

    constant V_BACK_PORCH : natural := 33;

    constant V_ACTIVE_VIDEO : natural := 480;

    constant V_FRONT_PORCH : natural := 10;

    -- Señales de temporización horizontal y vertical

    signal h_counter : natural range 0 to (H_SYNC_CYCLES + H_BACK_PORCH + H_ACTIVE_VIDEO + H_FRONT_PORCH);

    signal v_counter : natural range 0 to (V_SYNC_CYCLES + V_BACK_PORCH + V_ACTIVE_VIDEO + V_FRONT_PORCH);

begin

    proceso_temporizacion : process(clk, reset)

    begin

        if reset = '1' then

            h_counter <= 0;

            v_counter <= 0;

            h_sync <= '0';

            v_sync <= '0';

        elsif rising_edge(clk) then

            -- Temporización horizontal

            if h_counter = H_SYNC_CYCLES + H_BACK_PORCH + H_ACTIVE_VIDEO + H_FRONT_PORCH - 1 then

                h_counter <= 0;

            else

                h_counter <= h_counter + 1;

            end if;

            -- Temporización vertical

            if h_counter = H_SYNC_CYCLES + H_BACK_PORCH + H_ACTIVE_VIDEO + H_FRONT_PORCH - 1 then

                if v_counter = V_SYNC_CYCLES + V_BACK_PORCH + V_ACTIVE_VIDEO + V_FRONT_PORCH - 1 then

                    v_counter <= 0;

                else

                    v_counter <= v_counter + 1;

                end if;

            end if;

            -- Generar señales de sincronización

            h_sync <= '1' when h_counter >= H_SYNC_CYCLES and h_counter < H_SYNC_CYCLES + H_BACK_PORCH else '0';

            v_sync <= '1' when v_counter >= V_SYNC_CYCLES and v_counter < V_SYNC_CYCLES + V_BACK_PORCH else '0';

            -- Generar señal de píxel de salida (simplemente un contador)

            pixel_out <= std_logic_vector(to_unsigned(h_counter, 8));

        end if;

    end process proceso_temporizacion;

end Behavioral;