Circuitos Digitales - AYUDA URGENTE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador_comp_logicas is

    Port (

        CLK     : in STD_LOGIC; -- Reloj

        RESET   : in STD_LOGIC; -- Reset del contador

        Count   : out STD_LOGIC_VECTOR(5 downto 0) -- Salida del contador

    );

end contador_comp_logicas;

architecture Behavioral of contador_comp_logicas is

    signal internal_count : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- Registro interno del contador

    signal enable_next : STD_LOGIC; -- Habilitar siguiente incremento

    -- Compuertas lógicas para determinar cuándo habilitar el siguiente incremento

    signal enable_0 : STD_LOGIC;

    signal enable_9 : STD_LOGIC;

    signal enable_19 : STD_LOGIC;

    signal enable_29 : STD_LOGIC;

    signal enable_39 : STD_LOGIC;

begin

    -- Habilitar el siguiente incremento en función de los valores de count

    enable_0 <= (internal_count = "000000");

    enable_9 <= (internal_count = "01001");

    enable_19 <= (internal_count = "10011");

    enable_29 <= (internal_count = "11001");

    enable_39 <= (internal_count = "11111");

    -- Combinación de las señales de habilitación

    enable_next <= enable_0 OR enable_9 OR enable_19 OR enable_29 OR enable_39;

    process (CLK, RESET)

    begin

        if RESET = '1' then

            internal_count <= "000000";

        elsif rising_edge(CLK) then

            if enable_next = '1' then

                internal_count <= STD_LOGIC_VECTOR(unsigned(internal_count) + 1);

            end if;

        end if;

    end process;

    Count <= internal_count;

end Behavioral;