Arduino - VHDL - errores en los "vectores"

 
Vista:
sin imagen de perfil
Val: 2
Ha disminuido su posición en 4 puestos en Arduino (en relación al último mes)
Gráfica de Arduino

VHDL - errores en los "vectores"

Publicado por William (1 intervención) el 19/06/2020 22:02:25
Ayudaa!! estoy haciendo un Procesador simple en vhdl pero me salen errores en los "vectores"
aquí dejo el código, es del libro de "Fundamentos de logica digita con diseno en vhdl"

Código del procesador:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.ALL;
use work.subccts.ALL;
 
entity proc is
    PORT(Data    :IN     std_logic_vector(7 downto 0);
         Reset,w :IN     std_logic;
         Clock   :IN     std_logic;
         F,Rx,Ry :IN     std_logic_vector(1 downto 0);
         Done    :BUFFER std_logic;
         BusWires:INOUT  std_logic_vector(7 downto 0));
end proc;
 
architecture Behavioral of proc is
    SIGNAL Rin, Rout : std_logic_vector(0 to 3);
    SIGNAL Clear, High, AddSub: std_logic;
    SIGNAL Extern, Ain, Gin, Gout, FRin : std_logic;
    SIGNAL Count, Zero : std_logic_vector(1 downto 0);
    SIGNAL T,I,X,Y : std_logic_vector(0 to 3);
    SIGNAL R0,R1,R2,R3 : std_logic_vector(7 downto 0);
    SIGNAL A,Sum,G : std_logic_vector(7 downto 0);
    SIGNAL Func,FuncReg : std_logic_vector(1 to 0);
 
begin
    Zero <= "00"; High <= '1';
    Clear <= Reset OR Done OR(NOT w AND T(0));
    counter: upcount PORT MAP (Clear, Clock, Count);
    decT: dec2to4 PORT MAP (Count, High, T);
    Func <= F & Rx & Ry;
    FRin <= w AND T(0);
    functionreg: regn GENERIC MAP (N => 6)
                       PORT MAP (Func, FRin, Clock, FuncReg);
   decI: dec2to4 PORT MAP(FuncReg(1 to 2), High, I);
   decX: dec2to4 PORT MAP(FuncReg(3 to 4), High, X);
   decY: dec2to4 PORT MAP(FuncReg(5 to 6), High, Y);
   Extern <=  I(0) AND T(1);
   Done   <= ((I(0) OR I(1)) AND T(1)) OR ((I(2) OR I(3)) AND T(3));
   Ain    <= (I(2) OR I(3)) AND T(1);
   Gin    <= (I(2) OR I(3)) AND T(2);
   Gout   <= (I(2) OR I(3)) AND T(3);
   AddSub <= I(3);
 
   RegCntl:
   FOR k IN 0 TO 3 GENERATE
        Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR
                  ((I(2) OR I(3)) AND T(3) AND X(k));
        Rout(k) <= (I(1) AND T(1) AND Y(k)) OR
                    ((I(2) OR I(3)) AND (( T(1) AND X(k)) OR (T(2) AND Y(k))));
   END GENERATE RegCntl;
 
   tri_extern: trin PORT MAP(Data, Extern, BusWires);
   reg0: regn PORT MAP(BusWires, Rin(0), Clock, R0);
   reg1: regn PORT MAP(BusWires, Rin(1), Clock, R1);
   reg2: regn PORT MAP(BusWires, Rin(2), Clock, R2);
   reg3: regn PORT MAP(BusWires, Rin(3), Clock, R3);
   tri0: trin PORT MAP(R0, Rout(0), BusWires);
   tri1: trin PORT MAP(R1, Rout(1), BusWires);
   tri2: trin PORT MAP(R2, Rout(2), BusWires);
   tri3: trin PORT MAP(R3, Rout(3), BusWires);
   regA: regn PORT MAP(BusWires, Ain, Clock, A);
   alu:
        WITH AddSub SELECT
            Sum <= A + BusWires WHEN '0',
                    A - BusWires WHEN OTHERS;
        regG: regn PORT MAP (Sum, Gin, Clock, G);
        triG: trin PORT MAP (G,Gout,BusWires);
 
END Behavioral;

Código subccts:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package subccts is
        COMPONENT regn--registro
            GENERIC(N:INTEGER := 8);
            PORT(R         :IN std_logic_vector(N-1 downto 0);
                 Rin, Clock:IN std_logic;
                 Q         :OUT std_logic_vector(N-1 downto 0));
        END COMPONENT;
 
        COMPONENT trin -- buffers triestado
            GENERIC(N: INTEGER := 4);
            PORT(X  : IN std_logic_vector(N-1 downto 0);
                 E  : IN std_logic;
                 F  : OUT std_logic_vector(N-1 downto 0));
        END COMPONENT;
 
     COMPONENT  dec2to4-- decodificador binario dos a cuatro
        PORT(w  : IN std_logic_vector(1 downto 0);
             En  : IN std_logic;
             y  : OUT std_logic_vector(0 downto 3));
    END COMPONENT;
 
    COMPONENT  upcount --Contador ascendente
         PORT (Clear, Clock : IN     std_logic;
            Q          : BUFFER std_logic_vector(1 downto 0));
    END COMPONENT;
end subccts;
Valora esta pregunta
Me gusta: Está pregunta es útil y esta claraNo me gusta: Está pregunta no esta clara o no es útil
0
Responder